Toshiba Tapes Out High-Performance ASSP With Synopsys DFT Compiler SoCBIST
Deterministic Logic BIST Capability Reduces Test Cost for
Multimillion-gate .13 Micron Design
MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 17, 2003--
Synopsys, Inc. (Nasdaq:SNPS), the world leader in semiconductor
design software, today announced that Toshiba Corporation, a world
leading semiconductor manufacturer, has taped out a high-performance
digital image processor chip targeting consumer multimedia
applications using Synopsys DFT Compiler(TM) SoCBIST's deterministic
logic BIST capability. This six million gate device was designed using
Toshiba's advanced TC280 0.13 micron process. By partnering with
Synopsys to extend their design-for-test (DFT) flow for
next-generation LSI designs, Toshiba reduced overall test cost by
taking advantage of SoCBIST's ability to deliver a 10-times reduction
in tester time and more than 100 times reduction in test data volume.
"We partnered with Synopsys on our DFT flow, and DFT Compiler
SoCBIST enabled us to reduce tester time for our upcoming LSI design
by 12 times and test data volume by 900 times as compared to
traditional methodologies," said Seiichi Nishio, senior manager design
methodology, Toshiba Corporation Semiconductor Company. "We are very
pleased with the results we achieved with SoCBIST on our upcoming LSI
design. We expect to tape out multiple designs using SoCBIST before
the end of the year, and will continue to work with Synopsys to
develop advanced transition test and next-generation DFT
methodologies."
In its design flow, Toshiba uses Design Compiler(R), DFT Compiler
SoCBIST, Physical Compiler(R), PrimeTime(R), and TetraMAX(R) ATPG from
Synopsys' Galaxy Design Platform. Because DFT Compiler SoCBIST is an
integral part of Galaxy, Toshiba is able to achieve its overall design
objectives and achieve DFT closure smoothly and efficiently within the
same flow.
"We rely on Toshiba as one of our technology partners and driving
customers in the area of manufacturing test," said Antun Domic, senior
vice president and general manager, Synopsys Implementation Group.
"Toshiba provided key guidance to Synopsys on their requirements in
test quality, cost and diagnostics, and has built a very impressive
production methodology and design flow that fully and effectively
utilizes SoCBIST's capabilities. We look forward to our continued
collaboration with Toshiba and to advancing robust and
production-ready manufacturing test methods for their next-generation
products."
About Galaxy Design Platform
The Galaxy Design Platform is an open, integrated design
implementation platform with best-in-class tools, enabling advanced IC
design. Anchored by Synopsys' industry-leading IC implementation tools
and the open Milkyway(TM) database, the Galaxy Design Platform
incorporates consistent timing, SI analysis, common libraries, delay
calculation, and constraints from RTL all the way to silicon. The
Galaxy Design Platform helps reduce design time, decreases integration
costs and minimizes the risks inherent in advanced, complex IC design.
Synopsys Galaxy Test Automation Solution
Synopsys' Galaxy Test Automation solution, within the Galaxy
Design Platform, offers a comprehensive family of products for
mainstream to high-performance semiconductor designs. The
award-winning solution includes the advanced DFT Compiler, TetraMAX
ATPG and DFT Compiler SoCBIST products. The Galaxy Test Automation
solution incorporates capabilities that enable designers to achieve
DFT closure and sign off on the testability of their mainstream ASICs,
as well as reduce test cost and time and data volume for their most
complex designs. Galaxy Test offers a standards-based test automation
solution for core-based design that speeds the creation, integration,
and verification of test reuse-ready IP.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the world leader in electronic
design automation (EDA) software for semiconductor design. The company
delivers technology-leading semiconductor design and verification
platforms to the global electronics market, enabling the development
of complex systems-on-chips (SoCs). Synopsys also provides
intellectual property and design services to simplify the design
process and accelerate time-to-market for its customers. Synopsys is
headquartered in Mountain View, California and is located in more than
60 offices throughout North America, Europe, Japan and Asia. Visit
Synopsys online at http://www.synopsys.com/.
Synopsys, Design Compiler, Physical Compiler, PrimeTime, and
TetraMAX are registered trademarks of Synopsys, Inc., DFT Compiler,
MilkyWay, and Galaxy are trademarks of Synopsys, Inc. All other
trademarks or registered trademarks mentioned in this release are the
intellectual property of their respective owners.
CONTACT: Synopsys, Inc.
Nancy Renzullo, 650-584-1669
renzullo@synopsys.com
or
Edelman
Sarah Seifert, 650-429-2776
sarah.seifert@edelman.com
